1. Field of the Invention
The invention relates to a semiconductor package substrate having a plurality of bonding pads with a plated layer thereon, and a process of manufacturing the substrate. More particularly, the invention relates to a semiconductor package substrate in which a Ni/Au plated layer is formed on an exposed surface of a bonding pad, and a process of forming the Ni/Au plated layer on the exposed surface of the bonding pad of the semiconductor package substrate.
2. Description of the Related Art
Semiconductor package manufacturers have confronted great challenges to satisfy the requirements of product size reduction. A plurality of conductive traces, made of copper, for example, are formed on a substrate of a semiconductor package, and respectively extend to a plurality of bonding pads for signal and electrical current transmission. A Ni/Au layer is usually formed over the exposed surface of each bonding pad to improve electrical connection between gold wires, bumps or solder balls, chips or printed circuit board elements, and to further prevent oxidation of the bonding pads.
The bonding pads are the electrical contacts, for example, bump pads or presolder pads used to electrically connect a flip-chip package substrate to the chip, or a ball pad used to electrically connect the package substrate to the printed circuit board. A Ni/Au layer is usually formed over exposed surfaces of the bonding pads to prevent the bonding pads, which are usually made of copper, from oxidizing in the atmosphere.
Therefore, electrical connection of the bumps, presolder or solder balls to chips or the printed circuit board is improved.
In the prior art, the process of forming the Ni/Au layer over the bonding pads includes either chemically forming Ni/Au or electroplating Ni/Au. The chemical formation of a Ni/Au layer includes a non-electrical process such as the Nickel/Immersion Gold (EN/IG) process, which comprises electroless plating of the substrate in a Nickel bath to form a nickel layer on the bonding pad and immersion of the substrate in a gold bath to deposit a gold layer on the nickel layer. This process usually has disadvantages such as poor solderability and insufficient soldering strength, and further may form black pads and soldering with non-uniform-thickness. Soldering with non-uniform-thickness occurs when the nickel bath varies between temperature cycles. Even if the optimal operating conditions have been satisfied, the Gold layer often does not fully cover the nickel layer and thus the underlying copper layer may be externally exposed. Black pads are typically formed when the substrate is dipped in a gold bath while excessive oxidation is occurring. Specifically, gold atoms irregularly deposit on the nickel surface, resulting in a porous structure of a gold plated layer that, owing to a chemical battery effect on the underlying Nickel layer, causes continuous oxidation and aging of the underlying nickel layer. Problems such as non-uniform thickness and black pads deteriorate the connection and bonding of gold wires, solder bumps, presolder or solder balls to the bonding pads. Therefore, the reliability of the semiconductor package is reduced.
In order to avoid the above problems of chemical formation of the Nickel/Gold layer, another approach is to use the electroplating method. Referring to FIG. 1, a conventional process forms a plurality of plating wires 11 respectively on a plurality of bonding pads 10 of a semiconductor package substrate 1. A Ni/Au layer 12 is plated on the bonding pads 10 by means of the plating wires 11. However, the plating wires 11 undesirably occupy a portion of the routing area of the substrate 1, and further may generate noise due to an antenna effect when used at high frequency.
In order to solve the above problems, gold pattern plating has been proposed in the art. Referring to FIG. 2A, a conductive layer 21 is formed on either side of a substrate 2, being used to carry a semiconductor chip. A plurality of plated through holes (PTH) or blind vias (not shown) are formed through the substrate 2. A photoresist layer 22 is formed to cover a portion of the conductive layer 21 so that traces can be formed. The conductive layer serves as a path for electrical current. The conductive layer 21 not covered by the photoresist layer 22 is plated with a Ni/Au layer 23, as shown in FIG. 2B. Then, the photoresist layer 22 is removed, leaving the Ni/Au layer 23, as shown in FIG. 2C. The conductive layer 21 is patterned to form a trace layer 24 by using the Ni/Au layer 23 as an etching mask. Thereby, an exposed surface of the trace layer 24 is plated with a Ni/Au layer 23, as shown in FIG. 2D.
Although plating wires are not required in this case, the Ni/Au layer is necessary to form the whole trace layer over the bonding pads and the trace layer of the substrate. Since the material cost of the Ni/Au layer is expensive, material wastage of the Ni/Au layer increase the total production cost. Also, the solder mask subsequently formed to cover the substrate is not very compatible with the Ni/Au layer, which further reduces the reliability.
Therefore, there is a need for a simple process of manufacturing a semiconductor package substrate with a reduced cost which can avoid the problems of the prior art such as non-uniform thickness and black pads.